1. Field of the Invention
The invention relates in general to a wafer structure and a method for fabricating the same, and more particularly to a wafer structure having an electroplated layer and a method for fabricating the same.
2. Description of the Related Art
As electronic products become more and more popular in the market, more functions are provided into the products to meet consumers' demands. Along with the developing of multifunctional electronic products, more and more semiconductor packages are needed in the products. However, due to the miniaturization of volume and size of the products, semiconductor packages are facing severe tests with regard to heat dissipation and operational stability. Therefore, the quality of semiconductor packages becomes one of the crucial factors for maintaining product stability.
Of the semiconductor packaging technologies, examples of commonly used chip bonding technologies include flip-chip bonding, wire bonding and tape automated bonding. By way of these chip bonding technologies, the chips and the substrates are electrically connected. Among these bonding technologies, flip-chip bonding uses solder bumps as a connecting medium between the chip and the substrate. Compared with other bonding technologies, namely wire bonding and tape automated bonding, flip-chip bonding has the virtue of shorter electrical path and better quality in electrical connection, and therefore becomes an important research and development field for the manufacturers.
Generally, a wafer structure applied in the fabricating process of the semiconductor package includes a wafer, an under bump metallurgy (UBM) layer and a solder bump. The surface of the wafer has an electrical pad used as a terminal of electrical connection. The surface of the wafer is further covered and protected by a passivation layer. The passivation layer exposes part of the electrical pad. The UBM layer is normally sputtered on the pad and covers part of the passivation layer, so that the solder bump will not contact the electrical pad directly. The solder bump is disposed on the UBM layer. Normally, when performing the manufacturing steps with respect to heat treatment, such as the process of reflowing a solder layer to form the solder bump, thermal stress is generated between the material layers of the wafer structure. The passivation layer is usually relatively thin and susceptible to the stress, and therefore may easily crack. Under such circumstance, the solder material of the solder layer will contact the electrical pad via the damaged passivation layer and directly jeopardize the quality of semiconductor package.
In recent years, manufacturers have provided a wafer structure which forms a polymer layer on the passivation layer to avoid deteriorating of quality causing by the crack of the passivation layer. However, the way of stacking the polymer layer with the passivation layer makes the stacking of the UBM layer at the edges of the polymer layer and the passivation layer even more difficult. When the UBM layer is sputtered on the electrical pad, the improper stacking may easily occur at the edges of the polymer layer and the passivation layer. Referring to FIG. 1, a perspective of conventional UBM layer having improper stacking is shown. The passivation layer 13 is disposed on the wafer 11. The polymer layer 15 is disposed on the passivation layer 13. An indent 16(1) is formed between the edge of the passivation layer 13 and the edge of the wafer 11, and another indent 16(2) is formed between the edge of the polymer layer 15 and the edge of the passivation layer 13. When the UBM layer 17 is sputtered on the polymer layer 15, the passivation layer 13 and the wafer 11, improper stacking may easily occur at the indents 16(1) and 16(2) and affect the quality of the bonding between the solder bump and electrical pad. To the worse, the materials of the electrical pad and the solder bump may even spread into one another at the location of improper stacking, making the solder bump brittle or making the metallic material of the electrical pad generate metal void defect.